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**images**

**CSEQP**

**07A3EC16**

**DIGITAL**

**LOGIC**

**DESIGN**

(a) Find the decimal equivalent of the following two’s complement numbers. i. 11111 ii. 10001 iii. 01010 iv. 10011 v. 10101 (b) Explain about error Detecting code with example. [10+6] 2. (a) Simplify each of the following expressions i. ABCD + A BCD + CD ii. (A + B) (A + B + D) (B + C + D) (b) Explain about positive and Negative **LOGIC** in binary signals. [8+8] 3.

http://www.pvpsiddhartha.ac.in/im ... 07A3EC16-DIGITAL-LOGIC-DESIGN.pdf

Size: 43 Kb Pages: N/A Date: 2011-10-27

**images**INFQP R059210504

**DIGITAL**

**LOGIC**

**DESIGN**

3 II B.Tech I Semester Supplementary Examinations, February 2007 **DIGITAL** **LOGIC** **DESIGN** ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. i.

http://www.pvpsiddhartha.ac.in/im ... 59210504-DIGITAL-LOGIC-DESIGN.pdf

Size: 117 Kb Pages: 8 Date: 2012-11-10

**DIGITAL**

**LOGIC**

**DESIGN**

4 II B.Tech I Semester Regular Examinations, November 2006 **DIGITAL** **LOGIC** **DESIGN** ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1.

http://www.pvpsiddhartha.ac.in/im ... 59210504-DIGITAL-LOGIC-DESIGN.pdf

Size: 118 Kb Pages: N/A Date: 2011-10-31

**images**

**CSEQP**R059210504

**DIGITAL**

**LOGIC**

**DESIGN**

Repeat with a NAND SR latch. [6+10] ⋆⋆⋆⋆⋆ 2 of 2 Code No: R059210504 Set No. Convert the following to Binary and then to gray code.

http://www.pvpsiddhartha.ac.in/im ... 59210504-DIGITAL-LOGIC-DESIGN.pdf

Size: 118 Kb Pages: N/A Date: 2011-12-22

**DIGITAL**quiz3 spring07

**DIGITAL** **LOGIC** Design
Quiz 3
5/12/2007
Design 4-bit magnitude comparator circuit using 4-bits adder/subtractor circuit and any other necessary
digital **LOGIC** gates. Assume that both inputs number are positive.

http://www.cs.kent.edu/~ztamimi/pdf/digital-quiz3-spring07.pdf

Size: 7 Kb Pages: 1 Date: 2013-01-10

**DIGITAL**

**LOGIC**

**DESIGN**

Observe the output using **LOGIC** analyzer. VHDL assignments (Write VHDL code and simulate) 5) Two bits **DIGITAL** comparator. 6) Four bit ALU for minimum four arithmetic and Logical operations. 7) D f/f and JK f/f (using synchronous and asynchronous reset inputs). 8) Four bits UP/DOWN ripple counter using mode control. 9) Four bit synchronous counters using flip flop. 10) Study of various parameters of logical families and comparative study of TTL and CMOS.

http://www.indiraicem.ac.in/pdfs/ ... s/SE/Digital%20Logic%20Design.pdf

Size: 82 Kb Pages: 1 Date: 2012-10-21

**DIGITAL**

**LOGIC**

**DESIGN**

RQ.4 (a)Design sequential counter as shown in the state diagram usingK flip-flops 07 000 001 010 110 100 011 111State and explain the features of register transfer **LOGIC** 07Q.5 (a)RQ.5 (a)Explain the **DESIGN** ofArithmeticLogic

http://gtuinfo.in/Files/ExamPaper ... 0701-DIGITAL%20LOGIC%20DESIGN.pdf

Size: 94 Kb Pages: 2 Date: 2012-07-15

**DIGITAL**

**LOGIC**

**DESIGN**

3 SYSTEM OPERATION AND DESIGNS Our system operation has been illustrated in figure 1. Descrip- Fig. 2. Entrance gate counter system tions of some of the segments are given below: 3.1 Counter and Sensor System We have used modified positive edge triggered counter sys- tems for counting the number of people present in the space. We have used two sensor systems (e.g. The pulses needed to be shaped according to the operating frequency of counters.

http://www.ijser.org/researchpape ... em-Using-Digital-Logic-Design.pdf

Size: 544 Kb Pages: 5 Date: 2012-11-13

**DIGITAL**

**LOGIC**

**DESIGN**

OR Q.4 (a) With **LOGIC** diagram explain the operation of 4 bit binary ripple counter. Explain the 07 count sequence. How up counter can be converted into down counter? (b) Prepare a detailed note on: Instruction Codes. 07 Q.5 (a) What is scratchpad memory? With diagram explain the working of a processor unit 07 employing a scratchpad memory. (b) Briefly explain control organization. With diagram explain control **LOGIC** with one 07 flip-flop per state.

http://www.gtuinfo.in/Files/ExamP ... 0701-DIGITAL%20LOGIC%20DESIGN.pdf

Size: 99 Kb Pages: 1 Date: 2011-11-04

**DIGITAL**

**LOGIC**

**DESIGN**

a) Tabulate the PLA programming table for the following Boolean function. A(x,y,z) = ∑m(0,2,3,7) B(x,y,z) = ∑m(1,3,4,6) C(x,y,z) = ∑m(1,4) Draw and explain the relevant **LOGIC** diagram. (8M+7M) b) Explain in brief, about **LOGIC** construction of 32x4 ROM. Draw and explain the relevant **LOGIC** diagram. 7. a) What is meant by the term ‘edge triggered’?

http://kietcse.weebly.com/uploads ... 12770546/digital_logic_design.pdf

Size: 262 Kb Pages: 8 Date: 2012-10-21